----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    PWM_TOP 
-- Module Name:    PWM_TOP 
-- Project Name:   PWM
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity PWM_TOP is
	port(
		i_sys_clk: in STD_LOGIC;       --系统时钟输入
		i_sys_rst: in STD_LOGIC;	    --系统复位输入
		i_ext_trig: in STD_LOGIC;      --输入
		o_compare_result: out STD_LOGIC	
	);
end entity PWM_TOP;

architecture behavior of PWM_TOP is
	
	component FREQUENCY_DIVIDER is
	generic(
		sys_clk_fre_value: INTEGER := 50000000;
		div_clk_fre_value: INTEGER := 100000
	);
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;	
		o_div_clk: out STD_LOGIC	
	);
	end component;
	
	component PWM_COUNTER is
	generic(
		cnt_mod_value: INTEGER := 100
	);
	port(
		i_pwm_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;	
		o_pwm_val: out STD_LOGIC_VECTOR (7 downto 0) 	
	);
	end component;	
	
	component PWM_VALUE_SET is
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;
	   i_ext_trig: in STD_LOGIC;	
		o_compare_set_value: out STD_LOGIC_VECTOR (7 downto 0)
	);
	end component;	
	
	component PWM_COMPARATOR is
	port(
		i_compare_value: in STD_LOGIC_VECTOR (7 downto 0);
		i_compare_set_value: in STD_LOGIC_VECTOR (7 downto 0);
		o_compare_result: out STD_LOGIC
	);
	end component;
	signal w_sys_rst: STD_LOGIC;
	signal w_pwm_clk: STD_LOGIC;
	signal w_ext_trig: STD_LOGIC;
	signal w_pwm_val: STD_LOGIC_VECTOR (7 downto 0);
	signal w_compare_set_value: STD_LOGIC_VECTOR (7 downto 0);
begin
	w_sys_rst <= NOT i_sys_rst;
	w_ext_trig <= NOT i_ext_trig;
	U1: FREQUENCY_DIVIDER port map (	i_sys_clk => i_sys_clk, 
												i_sys_rst => w_sys_rst, 
											   o_div_clk => w_pwm_clk
												);      --分频器模块
	U2: PWM_COUNTER port map( i_pwm_clk => w_pwm_clk,
									  i_sys_rst => w_sys_rst,	
									  o_pwm_val =>w_pwm_val	
									);               --LED计数器模块
	U3: PWM_VALUE_SET port map( i_sys_clk => i_sys_clk,
										 i_sys_rst => w_sys_rst,
										 i_ext_trig => w_ext_trig,	
										 o_compare_set_value => w_compare_set_value
										);                --
	U4: PWM_COMPARATOR port map( i_compare_value => w_pwm_val,
										  i_compare_set_value => w_compare_set_value,
										  o_compare_result => o_compare_result
									);							--		
end architecture behavior;
